Date: 14/05/2010

Real Intent's new version of design verification tool adds VHDL checks

Real Intent is shipping its new version of Ascent Lint Version 1.3 added with capability to do VHDL checks to its existing Verilog checks. Lint performs syntax and semantic Hardware Description Language (HDL) lint checks for SoC class VLSI designs. It said to have extremely fast engine and low noise report for debugging electronic designs.

Ascent Lint 1.3 adds lint checking for VHDL in the following categories:

Ambiguous modeling
Differences between simulation and synthesis semantics
Naming and RTL coding conventions
VHDL subset restrictions to enforce modeling clarity and reduce unnecessary complexity
Operations with hidden or expensive implementation costs
Downstream tool flow issues
Network and connectivity checks for clocks, resets, and tristate-driven signals
Testability

"The customer response to the initial deployments of Ascent Lint has been universally very positive," commented Pranav Ashar, Chief Technology Officer at Real Intent. "The feedback is that it is extremely easy to set up and more than an order of magnitude faster than competitive products. Ascent Lint 1.3 builds on this platform to deliver VHDL support. In addition, a key focus in this release has been to deliver an unprecedented level of usability. We are confident that with this combination of very high performance and usability, Ascent Lint 1.3 will provide compelling value in the front-end of any verification flow."

Availability: Now