Date: 17/10/2011

Clock translators ICs o/ps 2 kHz-1.25 GHz with sub-400-fs RMS jitter on 12 kHz to 20 MHz

Analog Devices, Inc. has introduced two fully programmable jitter attenuating clock translators ICs that perform frequency translations for a wide range of wired communications applications -- including Synchronous Ethernet and SONET/SDH optical networks -- that require low jitter, fast time to market and cost effectiveness,. The AD9557 dual-input multiservice line card adaptive clock translator and the AD9558 quad-input multiservice line card adaptive clock translator translate any standard input frequency to any standard output frequency from 2 kHz to 1.25 GHz with sub-400-fs RMS total jitter on 12 kHz to 20 MHz.

ADI says the new clock translator ICs doesn't require additional VCXOs (voltage-controlled crystal oscillators) as in traditional PLL designs.

ADI explains that network line card designers can use same component in different board designs because of its built-in programmability of the AD9557 and AD9558 clock translators supports loop bandwidth from 0.1 Hz to 5 kHz. The AD9557 and AD9558 clock translators integrate an on-chip, low-phase-noise, frequency-agile VCO (voltage-controlled oscillator) and loop filter along with dynamic adaptive clock support. Adaptive clocking allows the DPLL (digital PLL) divider ratios to be changed while the DPLL is locked. This enables the frequency value at the output to be dynamically adjusted by up to +/- 100ppm from the nominal output frequency without manually breaking the loop and reprogramming the part with a sub 0.1 ppb step in frequency resolution. This adaptive clock function is used for applications such as SDH to OTN mapping/demapping and asynchronous mapping/demapping. The two devices are pin- or soft-pin pre-configured to support popular SONET/SDH, Ethernet, Synchronous Ethernet and Fiber Channel frequencies, while SPI (serial port interface) and I2C ports are available to program customized input-to-output frequency translation.

Key features of the AD9557 and AD9558 adaptive clock translators include:
Supports GR-1244 Stratum 3 stability in holdover mode
Provides smooth reference switchover with virtually no disturbance on output phase.
Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 Systems.
Supports ITU-T G.8262 Synchronous Ethernet slave clocks.
Supports ITU-T G.823, G.824, G.825, and G.8261.

The AD9557 and AD9558 clock translators available at 6 mm x 6 mm and 9 mm x 9 mm in size, respectively. The AD9557 features two reference inputs (single-ended or differential) and two pairs of clock outputs. Each output pair is configurable as a single differential LVDS/HSTL output or as two single-ended CMOS outputs. The AD9558 offers the same features but with four reference inputs and six pairs of clock outputs.

Availability, Pricing and Complementary PartsProduct Availability Temperature Range Price Each Per 1,000 Packaging
AD9557 Full Volume
Production Now -40°C to 85°C $15 40-lead LFCSP
6 mm x 6 mm
AD9558 Full Volume
Production Now -40°C to 85°C $16.25 64-lead LFCSP
9 mm x 9 mm
AD9577 Sampling
Now -40°C to 85°C $7.23 40-lead LFCSP
6 mm x 6 mm


The asynchronous AD9577 clock generator with dual PLLs complements the AD9557 and AD9558 clock translators by providing key elements of the clock tree for various applications. It is asynchronous clock solution for oscillator replacements and generates local clocks for processors, FPGAs, or PHYs in SONET/SDH, Synchronous Ethernet applications, Ethernet enterprise switches, core/edge router fabric cards and line cards as well as in packet transmission networks (PTN) and fiber channel applications.