Analog IPs for GF 12LP FinFET platform
Analog chip design IPs such as integer and Fractional Phase-Lock Loop (PLL), ring oscillator based PCIe 2/3 PLL, Process Voltage and Temperature (PVT) sensors, and Power on Reset (POR) circuitry and LC oscillator based PCIe 4/5 PLL for GF's 12LP platform and 12LP+ 12LP+ launched by IP supplier Analog Bits. The applications targeted by these Ips cover mainly high-growth cloud and edge AI related semiconductor design.
"Our collaboration with Analog Bits is focused on enabling our mutual customers with proven IP to deliver innovative next-generation chip designs," said Mark Ireland, vice president of Ecosystem and Design Solutions at GF. "The availability of Analog Bits' IP on GLOBALFOUNDRIES 12LP platform and12LP+ solution enables customers to further differentiate their products in AI, cloud, and high-end consumer applications. "GLOBALFOUNDRIES has been a good partner for Analog Bits," said Mahesh Tirupattur executive vice president at Analog Bits. "We are excited about the adoption and usage of our analog IP portfolio on GLOBALFOUNDRIES most advanced FinFET platform to address evolving AI requirements and the growing applications creating urgent demand for high-performance SoCs."