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  Date: 22/01/2018

Achronix embedded FPGA IP for SoCs and ASICs Si-verified on TSMC 16NM FinFET+

Achronix Semiconductor said it completed full silicon verification of its Speedcore eFPGA production validation chip built on TSMC 16nm FinFET+ process technology. Achronix has done rigorous bench and ATE tests covering full operating conditions to verify the complete functionality of the Speedcore test chip.

Achronix Speedcore IP designed specifically to be embedded in SoCs and ASICs, is well accepted in the market and is generating lot of revenue. Achronix revenue grew more than 700% year over year and exceeded $100 million, driven by sales of its Speedster22i FPGA family and licensing for its Speedcore eFPGA IP.

It is defined as fully permutable architecture tech with range of densities of 10,000 look-up-tables (LUTs) to two-million LUTs and large amounts of embedded memory and DSP blocks. , Speedcore eFPGA IP inside a SoC makes it hardware programmable so that they can have customized hardware accelerators which can be reprogrammable. Speedcore LUTs, RAM blocks and DSP64 blocks can be assembled like building blocks to create the optimal programmable fabric for any given application.

Achronix claims compared to standalone FPGAs, Speedcore eFPGAs deliver smaller die area, higher performance, lower power and lower overall system costs.

“The demand for Speedcore eFPGA technology has been growing exponentially since Achronix announced its availability a little over a year ago,” says Steve Mensor, vice president of marketing at Achronix. “Many companies interested in Speedcore eFPGA requested a platform to test their hardware acceleration algorithms as one of their sign-off criteria. The Speedcore16t Validation platform is an excellent tool that gives companies the ability to run their complex designs at 500MHz in hardware before finalizing their Speedcore requirements for their SoC.”

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